1. Field of the Invention
The invention relates generally to methods for forming bipolar transistor devices. More particularly, the invention relates to methods for forming bipolar transistor devices with enhanced performance.
2. Description of the Related Art
Semiconductor products often employ either or both of bipolar transistors and field effect transistors as switching devices or signal processing devices within electrical circuits. Digital semiconductor products generally employ field effect transistors while analog semiconductor products often employ bipolar transistors or bipolar complementary metal oxide semiconductor transistors (i.e., bipolar transistors in conjunction with field effect transistors).
Bipolar transistors are generally more complex to fabricate in comparison with field effect transistors. For that reason they are often difficult to fabricate with enhanced performance. In addition, such difficulties in fabrication are often more pronounced as bipolar transistor device dimensions are reduced.
It is thus desirable to provide methods for forming bipolar transistors with enhanced performance. The present invention is directed towards that object.
Various bipolar complementary metal oxide semiconductor transistors having desirable properties, and methods for fabrication thereof, have been disclosed in the semiconductor product fabrication art.
Included but not limiting among the methods are those disclosed within: (1) Lee, in U.S. Pat. No. 5,516,718 (a bipolar complementary metal oxide semiconductor transistor fabrication method that employs a polysilicon layer as a ion implant channeling reduction layer); (2) Robinson et al., in U.S. Pat. No. 5,541,120 (s bipolar complementary metal oxide semiconductor transistor fabrication method that employs annular insulator filler rings separating polysilicon emitter and extrinsic base regions); and (3) Naem, in U.S. Pat. No. 6,399,455 (a bipolar complementary metal oxide semiconductor transistor fabrication method that provides an ultra-small polysilicon emitter layer).
The disclosures of each of the foregoing references are incorporated herein fully by reference.
Desirable are additional methods for forming bipolar transistors and bipolar complementary metal oxide semiconductor transistors with enhanced performance.
The invention is directed towards the foregoing object.
A first object of the invention is to provide a method for fabricating a bipolar transistor.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the bipolar transistor is fabricated with enhanced performance.
In accord with the objects of the invention, the invention provides a method for fabricating a bipolar transistor.
The method first provides a semiconductor substrate having formed therein: (1) an intrinsic base region of a first polarity which includes a surface of the semiconductor substrate; (2) an extrinsic base region of the first polarity formed adjoining the intrinsic base region; and (3) a collector region of a second polarity opposite the first polarity formed within the semiconductor substrate and beneath the intrinsic base region. The method next provides for forming a polysilicon emitter layer upon the intrinsic base region and separated from the extrinsic base region. The method still further provides for first implanting a portion of the intrinsic base region interposed between the extrinsic base region and the polysilicon emitter layer with an amorphizing non-active dopant. The method finally provides for next implanting the polysilicon emitter layer with an active dopant to form a doped polysilicon emitter layer.
The invention provides a method for fabricating a bipolar transistor with enhanced performance.
The invention realizes the foregoing object within the context of fabricating a polysilicon emitter bipolar transistor having a polysilicon emitter layer formed upon an intrinsic base region within a semiconductor substrate and separated from an extrinsic base region formed adjoining the intrinsic base region. The invention provides for: (1) first implanting a portion of the intrinsic base region interposed between the extrinsic base region and the polysilicon emitter layer with an amorphizing non-active dopant; prior to (2) next implanting the polysilicon emitter layer with an active dopant to form a doped polysilicon emitter layer.